Francesco Conti received his PhD in Electronics, Telecommunications and Information Technology Engineering in 2016 from the Department of Electrical, Electronic and Information Engineering (DEI) of the University of Bologna, under the supervision of Prof. Luca Benini. Since September 2025 he has been an Associate Professor at DEI, after five years as an Assistant Professor (in tenure track since 2022). From 2016 to 2020 he was a post-doctoral researcher at the Integrated Systems Laboratory (IIS) of ETH Zürich, Switzerland, in the Digital Systems group led by Prof. Luca Benini, with which he remained associated as an external consultant until 2025. He was also a consultant for GreenWaves Technologies (2020–2024) and, since 2026, for Fondazione Chips-IT.
Prof. Conti's research focuses on the deployment of advanced perceptive and generative AI algorithms on heterogeneous, accelerator-rich SoCs, which he pursues jointly from a hardware perspective (design of novel accelerated SoCs and neural processing units) and a software one (development of deployment tools). He is one of the most senior members of the open-source PULP platform team, spanning ETH Zürich and the University of Bologna, and is the main coordinator of its hardware acceleration activities. As RTL designer, system architect and front-end developer he has contributed to the tape-out of more than 15 successfully working SoC prototypes — including Vega, Marsellus and Siracusa, presented at ISSCC and JSSC — and, with GreenWaves Technologies, of two commercial SoC products, for which he designed the HWCE and NE16 neural engines.
He is the scientific coordinator for several EU and international research projects at the University of Bologna, and supervises or co-supervises 18 PhD students between Bologna and Zürich.
Prof. Conti is an IEEE Senior Member and has appeared in the Stanford/Elsevier Top 2% Scientists List in 2024 and 2025 in the Computer Hardware & Architecture category (1st percentile). He serves on the technical program committees of ISSCC and ESSERC and is an Associate Editor of IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. His work has received several awards, including the 2018 HiPEAC Technology Transfer Award, the 2020 IEEE CAS Darlington Award, and Best Paper Awards at CODES+ISSS 2018, ISVLSI 2023 and IEEE JETCAS 2026. He has authored publications collecting more than 3,400 citations (h-index 31, Scopus).